1. Field of the Invention
The present invention relates to a method for detecting a faulty memory cell of a programmable semiconductor device. More particularly, the present invention relates to a method for detecting a delayed access time caused by its degraded isolation resistance of unprogrammed cell.
2. Description of the Related Art
A great many of programmable read only memories made by a semiconductor technology (referred to hereinafter as PROM) have been widely used in the electronic industry, and they can be classified by the type of the memory cells, such as a fuse-blown type, a junction-short type and an insulator-short type. The fuse-blown PROM is that in which the writing-in a memory cell is carried out by applying a high current therein to blow the fuse. The junction-short PROM, so-called diode type, is that in which the writing-in a memory cell is carried out by applying a high current therein to short the reverse p-n junction diode. The insulator-short PROM, so called condenser type, is that in which the writing-in the memory cell is carried out by applying a higher voltage than its break-down voltage to short the insulator made of, for example, a silicon dioxide, in place of the above-mentioned p-n junction diode.
As a representative prior art which supports the explanation of the present invention, a PROM of the p-n junction type shall be hereinafter described in detail. A general concept of a modern PROM of junction-short type is also described by the inventor et al. in a paper "A 40 ns 64 Kbit Junction-Shortening PROM", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL sc-19, No. 2, April 1984.
A memory cell of a junction-short type is shown in FIGS. 1. FIG. 1a schematically illustrates a vertically cross sectional view of a memory cell. FIG. 1b shows the equivalent circuit of the cell M.sub.0. A diode D, as a programmable element, and a reverse current stopper element Q operatively connected in series, compose the memory cell M.sub.0. The diode D is connected in a direction to block the current flow from the bit line. The reverse-current stopper Q is a p-n-p transistor connected in a direction to allow a current to flow from the bit line therethrough and through the diode D. This stopper element Q can be a diode, however, the description shall be given only for the case using a transistor, because the stopper element is not directly concerned with the present invention. As shown in FIG. 1a, the diode D is composed of n.sup.+ and p.sup.+ diffusion layers fabricated by ordinary n-p-n transistor technology. The p-n-p transistor Q consists of the p.sup.+ diffusion layer, which is common to the p-n junction diode, an n-epitaxial layer, and a p.sup.- substrate. An aluminum electrode (not shown in FIG. 1a) is provided as a bit line B.sub.0 on the n.sup.+ layer which is the cathode of the diode D. The common base of the transistor Q acts as a word line W.sub.0.
The memory cell M.sub.0 is addressed, namely selected, by applying a high level (referred to hereinafter as H) on the bit line B.sub.0 as well as a low level (referred to hereinafter as L) on the word line W.sub.0. For programming, namely writing-in an addressed cell, current pulses of 125 mA and 11 micro sec. are applied to the addressed cell through the bit line. This high current not only breaks down the reversely connected diode but also increases the temperature of the jucntion to result in a short. As for reading-out the cell, when a cell is addressed, and if the diode D has been previously shorted, namely programmed (referred to hereinafter as written-in), a current flows form B.sub.0 through D and Q to ground. If the diode D is non-conductive, namely not programmed (referred to hereinafter as unwritten-in), the above-metnioned current does not flow. Thus, the stored datum in the cell, "1" or "0", can be readed-out by sensing the existance of this current flow.
In FIG. 1c, there is shown the voltage-current characteristics between B.sub.0 and W.sub.0 of an addressed unwritten-in memory cell. This characteristics is dominantly affected by the degradation of the reverse diode D by its leakage, because the transistor Q is conductive. The ideal characteristics of a memory cell is shown by the curve (a), where the current is almost nothing as far as the applied voltage is below the breakdown voltage of normal 6 to 7 volt, and sharply increases when the applied voltage exceeds the breakdown voltage. This breakdown is caused by the Zenor-breakdown of the reverse diode D. The curve (b) and (c) show the characteristics of degraded memory cells each having so-called soft breakdown. The leakage is normally caused by lattice defects at the surface or abnormal diffusion. When this current leakage is large or the breakdown voltage is low, it is difficult to distinguish the leaky cell from a written-in cell. And, in a worst case, this results in a reading-out error. Therefore, the leakage below a specified voltage of the reverse diodes must be tested and rejected at the production process of the PROM.
Another problem caused by this leakage of the unwritten-in diode is concerned with the access time, the delay time for reading-out. A leaky unwritten-in cell has a longer access time than that of the normal cell. The mechanism of this delay, the longer access time, is as follows. Before a bit line is addressed, the voltage level of the bit line B.sub.0 is L. At a moment at which the bit line is addressed,t he bit line starts to rise up to the H level, receiving a current from a power supply of a voltage V.sub.cc through a fixed resistor R.sub.1 (FIG. 2). However, each bit line is destined to have a stray capacity C.sub.0 parallel to the cell. Because of the time constant of the charging resistor R.sub.1 and the stray capacity C.sub.0, the voltage rise on the bit line is gradual as shown by the curve C.sub.1 in FIG. 3. Then, if the cell has a leakage, the charging current into the capacity is reduced by the amount of the leakage and also the charge in the capacity is lost through this leakage. Accordingly, not only is the voltage at a steady state lower than that of a normal cell, but also the speed of the voltage rise is slower (as shown by the curve C.sub.2) than that of a normal cell (as shown by the curve C.sub.1). The access operation of a memory cell is completed when the bit line reaches the threshold level, and the output level of the output buffer is changed. Thus, a leaky cell results in a longer delay of completion of the access operation than that of the normal cell.
When the integration of PROM was not as large and the access time was not as severe as todays, the access delay caused by a small leakage as above mentioned was not very serious. However, as the PROM became larger in memory capacity, the variation of characteristics of the cells became larger, and the probability of producing cells having a small leakage, like curve (b), has is also increased. Therefore, amethod to effectively detect the faulty cell caused by a small leakage must be imperatively established.
In general, in order to discriminate a leaky cell, a DC (direct current) test may be used, where a limiting current level, as shown by TL in FIG. 1c, is specified. However, the value of TL can not be reduced as much as required, because the possible lowest value of TL is limited by the peripheral circuit in use.
The reason why the detectable lowest leakage current is limited is as follows. The constitution of a typical PROM is shown by the block diagram in FIG. 4. The output terminal O.sub.0 is used in three ways, namely for reading-out, writing-in and testing. Testing of a cell is done by applying a voltage on the output terminal O.sub.0 in order to inject a current from an external tester, and sensing the current flowing thereinto. The number of output terminals that are provided that as many as the number of readed-out bit lines, but only one terminal O.sub.0 is referred to, because one terminal is enough to explain the principle of the cell test. PROG shown in FIG. 4 denotes a programming circuit, a circuit for writing-in a cell. A circuit diagram relating to one memory cell of the programming circuit PROG is schematically illustrated in FIG. 5 in detail. Further in FIG. 4, XADD denotes a X-address buffer, and D/D denotes a decoder/driver all of which are equivalent to the word driver WD in FIG. 5. YADD denotes a Y-address buffer, which, in case of reading-out, controls the multiplexer MPX to select the bit line of the cell to be readed-out, as well as in case of writing-in, and controls the programming circuit PROG to select the bit line to the cell to be written-in. CE denotes a circuit for enabling, namely activating, the output buffer OUT, at a chip-enable state. TW and TB denote respectively a test word line and a test bit line, by each of which test cells are operatively connected to be addressed. These test cells are written-in cells which have been provided in addition to the ordinary memory cell for testing purpose.
Function of the programming circuit PROG, used for testing a cell, is described hereinafter. As shown in FIG. 5, the circuit PROG is composed of transistors Q.sub.1, Q.sub.2 mutually in a Darlington connection, a resistor R, a diode D.sub.1 both of which are for pulling up the collectors of these transistors to a power source V.sub.cc, and a constant-current power source CS. (If the collectors are floated without being pulled-up, a parasitic capacity of the collectors may cause a malfunction of the circuit.) The output terminal is operatively connected to the collectors of the Darlington circuit through a diode D.sub.2, which prevents a current from flowing toward the outside. In this circuit, when the word line W.sub.0 is addressed by the word decoder WD as well as the bit line B.sub.0 is addressed by NAND.sub.1 controlled by the combination of signals in Y-address buffer YADD, the transistors become conductive by a current I.sub.1 (0.3 mA) supplied from the current source CS. Thus a current I.sub.2 from the power source V.sub.cc through the resistor R and the diode D.sub.1, together with the current I.sub.1, are ready to flow into the bit line B.sub.0. The resistor R is of approximately 1 K ohm, for example, so the current I.sub.2 is of approximately 2 mA. At this state, if the addressed cell M.sub.0 is conductive, namely previously written-in or having a defectively large leakage, the current I.sub.1 +I.sub.2 flows into the bit line B.sub.0. If the addressed cell M.sub.0 is unwritten-in, this current does not flow thereinto. As previously described, the test of the cell is done by sensing a current flowing into the terminal O.sub.0 while injecting a current into this terminal from an external tester. However, if the leakage current of the cell under test is as low as I.sub.1 +I.sub.2, no current can flow into the terminal O.sub.0, because the current I.sub.1 +I.sub.2 is already supplied from other sources. Thus, at the terminal O.sub.0 the external tester can only detect a current of more than I.sub.1 +.sub.2. This means that the lowest detectable level of the leakage current of the cell is TL=I.sub.1 +I.sub.2. Therefore, if its leakage current is lower than I.sub.1 +I.sub.2 the above-described DC method can not detect a faulty cell whose access time is so long as can not be disregarded.